Continued progress is being made in the integrated circuit technology with respect to higher speed switching circuits and more functions per chip. As a result, many integrated circuit chips now include plural functions, ranging in order of a magnitude greater number of functions than integrated circuits of a decade ago.
The Schottky Transistor Logic (STL) family of digital circuits represents a recent development in the integrated circuit technology for providing increased circuit speed and reduced supply voltage requirements. A Schottky-clamped or metal barrier junction in parallel with a transistor base-collector junction prevents the bipolar transistor from becoming saturated, thereby reducing base storage times and increasing switching speeds. Despite the improved circuit speed of this family of logic, the increased density of circuits within a chip can offset the advantage of higher switching speeds, thus negating the use of nonsaturating STL circuits. This is especially true when a logic gate or buffer must drive a large number of other circuits within the chip. As the output of a driving circuit is fanned out to a number of inputs of other circuits, the capacitive loading on the driving circuit is increased, thus degrading the operation of the STL circuits. The added capacitance is attributed in general to the stray capacitance between the interconnecting metallic conductors and the substrate, as well as to the junction capacitance of diodes and transistors connected to such conductors.
With the use of STL circuits as heretofore known, the circuit parameter most affected by stray load capacitance is the rise time of the waveform produced by the output of the driving circuit. Typical STL circuits, and particularly interstage buffer circuits, are constructed with an output driving structure having a pull-up resistor. As a consequence, the time constant in which the stray load capacitance can be charged to a particular level is directly related to the value of the pull-up resistor and the value of distributed capacitance. It can be seen that as the number of circuits driven by a buffer circuit increases, the output rise time thereof is correspondingly degraded.
From the foregoing, it may be seen that a need has arisen for an improved interstage buffer for driving multiple circuits in an integrated circuit chip. An associated need has arisen for an interstage driver circuit which has an output rise time parameter essentially independent of the nature of the capacitive load.